1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the present invention is directed to semiconductor chip designs and structures of inner leads of a lead frame in IC devices requiring dense arrangements of input and output connections.
2. Description of the Related Arts
A semiconductor chip must have connectors such as electrode pads (also called `bonding pads`) for making electrical interconnections with an external world (e.g., lead frame leads). For these electrical interconnections, a wire bonding technology is widely used, by which electrode pads of the chip and the inner leads of a lead frame are coupled through metal wires, such as gold or aluminum bonding wires. Important parameters in the design of wire bonding structures include the maximum wire span, the electrode pad pitch, the lead pitch, and the arrangement of the electrode pads on a chip's active surface.
The maximum wire span (i.e., the maximum allowable distance between an electrode pad and an inner lead electrically coupled by a wire, without undue risk of short circuiting) is influenced, among other things, by the diameter of the bonding wire. The 100-D rule is generally applied to determine the maximum allowable wire span length. For example, if a wire has a diameter of 1.25 mil (=0.00125 in. or 32 micron), 125 mil of wire span is normally designed to be a maximum. The maximum wire span also depends on the distance between electrode pads and the edge of a lead frame pad (or die pad). One of the most important factors, however, in determining the maximum wire span is whether or not the bonding wires can endure the pressure of molding flow to prevent electrical shorts with neighboring wires. In the present semiconductor assembly industry, the maximum wire span is about from 180 to 200 mil, but it is desirable to have the wire span significantly shorter than this in order to avoid the above mentioned problems.
The electrode pad pitch is the distance between two adjacent electrode pads on the semiconductor chip along the electrode pad line, while the lead pitch is the distance between two inner leads of the lead frame. Both pitches are important in the bonding structure design. The required pad pitch and lead pitch are basically determined by how many electrical paths to the external device are needed in the IC device. The greater the number of the electrode pads (and therefore, also, inner leads), the finer the pad pitch and lead pitch need to be. The pad pitch also depends on other factors, such as; the size of the electrode pads, the size of a wire ball formed on the electrode pad, the distance between a capillary of a wire bonding head and neighboring wire ball, and the distance between the capillary and neighboring bonding wire. Presently, the minimum allowable pad pitch is about from 80 to 100 micron, and the minimum allowable lead pitch (determined in light of the manufacturable limits of the lead frame) is approximately 180 to 200 micron.
FIG. 1A shows a plan view of a lead frame suitable for use in packaging a semiconductor chip requiring high I/Os, according to the prior art, and FIG. 1B is an enlarged view of `A` of FIG. 1A. Referring to FIGS. 1A and 1B, a semiconductor chip 10 is attached to a die pad 12 of the lead frame, and the die pad 12 is coupled to side rail 17 of the lead frame by four corner tie bars 14. The tie bars 14 are used to suspend the die pad 12. (The chip 10 and lead frame are symmetrical about both an imaginary x and y axis, intersecting in the center of chip 10, therefore each corner is of identical construction and reference to one corner can be considered a reference to any of the four corner segments.) Inner leads 16 of the lead frame are electrically connected to electrode pads 20 of the chip 10 by bonding wires 18. The inner leads 16 extend radially inward toward four sides of the chip 10. This type of lead frame is employed in conventional quad surface mount packages such as QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and the like. These quad packages can provide more than two hundred I/O connections, and have outer leads formed as a gull-wing or a J-shape for surface mounting that allows higher mounting density than a pin insertion mounting method. Furthermore, the inner leads 16 have an inner lead tip line 13 which is not parallel to the side of the chip 10, but is instead slightly tilted outward, away from chip 10, at the central side regions. By doing this, more inner leads can be included than in a comparable parallel inner lead structure.
The semiconductor chip 10 conventionally employed in the quad type package has a plurality of electrode pads 20 arranged along electrode pad lines 21 in a rectangular form along the periphery of the chip active surface in order to accommodate very dense arrangements of I/O connections. Unfortunately, in the quad surface mount package, corner wires for connecting electrode pads formed on corners of the chip and inner leads near the tie bars 14 inevitably have very long wire span. For example, with reference to FIGS. 1A and 1B, in an exemplary embodiment of the prior art, the size of the chip 10 is 4675 .mu.m.sup.2, the pad pitch is a constant 75 .mu.m, and a 208 pin (or lead count) lead frame with lead pitch `lp` of 200 .mu.m is used. The resulting wire span S2 at the central region is 182 mil while the corner wire span S1 is 218 mil. These significantly longer corner wire may result in electrical shorting with neighboring corner wires during a wire bonding process or a molding process. In particular, the distance between the neighboring wires decreases toward the electrode pads, thus making electrical shorts more likely. In the above example, for instance, the resulting distance d1 is 97.6 .mu.m and the resulting distance d2 is 136.5 .mu.m, where d1 is taken at a position one-quarter of S1 from the electrode pads and d2 is taken at a position one-half of S1 away from the electrode pads.
Among the difficulties experienced by the prior art, is electrical short circuiting of nearby wires due to molding flow or wire sweep. The corner wires located on both sides of a gate G (through which a molten plastic is injected and flows perpendicularly past the long corner wires, see FIG. 1A) experience considerable force during molding, and thus, wire sweep and electrical shorting with adjacent wires tends to occur. In order to avoid this problem, another prior art semiconductor chip 10, as shown in FIG. 2, has an increased pad pitch of the corner electrode pads 22. With this structure, the distance between adjacent wires can be increased. For example, modifying the above exemplary chip and lead frame, when the corner pad pitch is increased to 120 .mu.m (compared to 75 .mu.m) the wire distances d3 and d4 (taken at the same locations along S1 as d1 and d2, respectively) are increased over d1 and d2 to 119.6 .mu.m and 151.2 .mu.m, respectively. However, a significant drawback of this prior art is that the increase of the corner pad pitch results in a larger chip size. This increase in chip size is obviously retrogressive against the miniaturization trend in the modern semiconductor industry, and thus undesirable.
Another example of the prior art is U.S. Pat. No. 5,466,968 which discloses a lead frame in which inner leads are arranged to turn by 90 degrees from the typical arrangement shown in FIG. 1A. With this structure of the inner leads, the leads are progressively closer to an IC chip toward tie bars of a lead frame, which allows the corner wires near the tie bars to be shortened.
As the integration of IC devices becomes higher, the number of input and output connections required in the IC device increases significantly. In particular, the number of I/O connections for logic and microprocessor devices continues to increase in proportion to the number of gates on the IC chip. Accordingly, there is a need in the semiconductor industry to further and more effectively overcome the problems and disadvantages described above, particularly in connection with the corner wires.